1. Field of the Invention
The present invention relates to a differential delay circuit for use in a voltage controlled oscillator employed in a phase lock loop, and more particularly, to a ring-type voltage controlled oscillator.
2. Description of the Related Art
A voltage controlled oscillator (VCO) varies an oscillation frequency in accordance with a voltage received from a phase locked loop (PLL). A resistor-capacitor (RC) multivibrator, or a ring oscillator, is typically employed as the VCO. The ring oscillator includes a plurality of inverters or differential delay cells connected in series with each other in the form of a ring, and oscillates with delay time.
In general, an oscillation signal of the VCO includes jitter due to internally and externally-generated noise. Internal noise sources include thermal noise and shot noise of active devices and passive devices of the VCO circuit. External noise is usually generated by a power supply, and can be attenuated by enhancing the power supply ripple rejection ratio using a differential-type delay cell.
A conventional VCO employing a differential delay circuit is schematically depicted in FIG. 1. In FIG. 1, the VCO includes a plurality of differential delay cells 1, 2, and 3 and a comparator 5. Each of the differential delay cells 1, 2, and 3 receives a differential input signal and outputs delayed signals. The comparator 5 compares the differential output signals of the final differential delay cell 3 in the series to determine the output logic level. In this manner, the VCO oscillates a pulse signal having a periodically inverted logic level.
FIG. 2 is a schematic diagram of a differential delay cell 1, 2, 3 of FIG. 1. Assuming the first differential input signal V.sub.IP is logic high and the second differential input signal V.sub.IN is logic low, transistor MP1 is turned off, or inactive, and transistor MP2 is turned on, or active. Thus, positive output V.sub.OP is high and negative output V.sub.ON is low. There is a propagation delay time between the input signals V.sub.IP and V.sub.IN and the output signals V.sub.OP and V.sub.ON. Assuming the first differential input signal V.sub.IP is low and the second differential input signal V.sub.IN is high, the positive output V.sub.OP becomes low and the negative output V.sub.ON becomes high, and there is again a propagation delay time between the input and the output signals. Resistance values of variable resistors R1 and R2 are variable in response to a control voltage V.sub.R, so that the resistance values, and therefore the output voltage levels, are maintained, even if the current supplied by the current source I.sub.SOURCE is varied.
In the above-described differential delay cell, the propagation delay time t.sub.d of the cell is expressed by: ##EQU1##
Where V.sub.PP denotes a peak-to-peak level of the differential input voltage, C.sub.L, or load capacitance, denotes the total parasitic capacitance of the output terminal of the differential delay cell, and I.sub.SOURCE denotes the current supplied by the current source.
As shown in Equation 1, the propagation delay time t.sub.d is proportional to the peak-to-peak level of the differential input voltage and inversely proportional to the current source I.sub.SOURCE. It is preferable to reduce the propagation delay time t.sub.d in order to increase the operation enabling frequency and dynamic range of the VCO. The propagation delay time t.sub.d can be reduced by decreasing the peak-to-peak level V.sub.PP of the differential input voltages, or by increasing the amount of the source current I.sub.SOURCE. However, if the peak-to-peak level V.sub.PP is reduced to less than a critical level, the comparator 5 is no longer sensitive enough to respond to the output of the delay cells. Thus, a method for reducing the peak-to-peak level V.sub.PP of the differential input voltages, without adversely affecting the operation of the comparator 5, is desired.
Referring to FIG. 2, variable resistors R1 and R2 include diode-connected transistors. However, over a certain range of control voltage, V.sub.R, the transistors operate non-linearly, until the transistors are fully activated and current flows. Thus, as shown in FIG. 3, the input/output characteristic of the delay cell of FIG. 2 includes distortion. Preferably, each of the output signals V.sub.ON, V.sub.OP is linearly varied when the voltage level of the positive differential input is the same as that of the negative differential input. However, before and after the switching level of the delay cell of FIG. 2, each of the output signals varies non-linearly, and the resulting differential output for the positive differential input is smaller than that for the negative differential input. This non-linear characteristic leads to unstable operation of the VCO.